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Questa’s core simulation and debug engine

The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF.

Comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.

  • Easy to use, fast time-to-debug through native assertions and a complete multi-abstraction and multi-language debug environment including transaction-level debug
  • Constrained-random stimulus generation to automate test development
  • High-performance, multi-language engine for the most sophisticated regression suites
  • Native advanced SystemVerilog testbench capabilities with OVM and UVM combined with unique debug function to ease the development and debug of advanced testbenches