Date(s) - 05/24/2018
11:30 am - 12:30 pm



Today’s designs rely heavily on a growing variety of complex industry standard interfaces that must be verified to ensure IP interoperability and system behavior. Mentor’s verification IP (VIP) improves quality and reduces schedule times by building Mentor’s protocol and methodology expertise into a library of reusable components that support many industry standard interfaces. This frees up engineering resources from having to spend time developing BFMs, verification components, or VIP themselves, enabling them to focus on the unique and high-value aspects of their design.

Who Should View

  • Verification engineers and managers

What You Will Learn

  • Rapidly generate verification IP components most common protocols use in UVM or OVM testbench environment
    • Use build in sequence items quickly create transaction on your protocol bus
    • Use built in transaction streams to view transactions in the wave window, raising abstraction level of debug
    • Identify critical protocol features and use VIP sequences and coverage to verify testing of these features
  • Rapidly generate memory models and quickly integrate them into any testbench using Mentor’s memory configurator software
    • Verify your memory controllers with assertions, coverage, and transaction level debug
    • Easily switch between primary and second source memory models using Mentor’s unique on-the-fly reconfiguration



Bookings are closed for this event.