Date(s) - 12/20/2018
11:30 am - 12:30 pm
Categories No Categories
The Universal Verification Methodology (UVM) is a standard verification methodology from the Accellera Systems Initiative that was developed by the verification community for the verification community. UVM represents the latest advancements in verification technology and is designed to enable creation of robust, reusable, interoperable verification IP and testbench components.
UVM Framework is a combination of a class library and a code generator, delivered as part of the Questa® Verification Solution, that enables you to build a UVM testbench within an hour. Providing an architecture and reuse methodology, it allows both experienced and new to UVM verification teams to assemble operational UVM testbenches as well as all the scripts needed to compile and run this testbench. The testbench can also include industry-standard Questa VIP components. This quick jumpstart allows the team to focus on verifying product features instead of the normally tedious work building a UVM TB from scratch.
With larger and more complex designs, the gap between design and verification has grown larger. Because of this the reuse of the testbench both in new projects and within different levels of the same project has become very desirable. One of the “promises” of UVM is achieving such reuse. However, in reality, UVM reuse has been limited. The UVMF provides this reuse of testbench agents both from block to chip level within the same project and from project to project.
What You Will Learn
- General UVMF testbench structure and benefits
- How UVMF greatly speeds creation of a UVM environment
- How UVMF facilitates Reuse of UVMF agents
- Vertically within a project – From block, to sub-system, to system
- Horizontally – Between projects
Who Should Attend
- FPGA/ASIC Design Engineer
- Verification Engineer
- Engineering Managers