Date(s) - 05/31/2018
11:30 am - 12:30 pm



Detect critical design errors and eliminate design respins caused by schematic errors by automating the process of board-level verification. Mentor’s Valydate for schematic integrity analysis provides the confidence that your design intent is implemented right the first time, regardless of the PCB design tools used.


Schematic design errors that result in costly design respins are easily caught by Mentor’s Valydate schematic integrity analysis, saving many hours of manual inspection and increasing design quality. Only Valydate fully inspects 100% of a schematic’s nets and verifies the entire system, including connections between boards.

What You Will Learn

  • Why schematic integrity analysis is the ONE step your design process is missing
  • How to eliminate 50-70% of design respins caused by schematic errors
  • How to avoid passing schematic errors on to layout, fab/assembly, testing, and final products
  • How schematic DRCs can save hundreds of hours of manual, visual inspection




Bookings are closed for this event.