Date/Time
Date(s) - 09/27/2018
11:30 am - 12:30 pm

Categories No Categories


Overview

When verification is not under control, project schedules slip, quality is jeopardized and the risk of re-spins soars. What’s required is a common platform and environment that provides all parties – system architects, software engineers, designers and verification specialists – with real-time visibility into the project. And not just to the verification plan, but also to the specifications and the design, both of which change over time.

There are three dimensions to any IC design project: the process, the tools and the data. Questa® offers a comprehensive approach to the problem with its verification management option that handles all within a scalable and modular solution.  With the flexibility which allows enabling technologies to be deployed either alongside current legacy verification environments, incrementally replace them in a modular fashion or benefit from the power and integration of the complete solution.

Verification management should be based around a structured process but also requires the tools to allow this process to be automated. Given the rise in design complexity, it’s no surprise that data management is increasingly the foundation of any verification management activities. Questa’s verification management capabilities are built upon the Unified Coverage Database (UCDB), which was architected for requirement storage. This allows all the relevant verification data to be stored in an extremely efficient format with open access.

 

What You Will Learn

  • How to close the loop between verification plans and verification using electronic closure to ensure you hit your market windows on schedule.
  • How to manage priorities, risk and keep resources on track.
  • How to reduce the volume of data within the process while still having full visibility into the progress of the project.
  • How to jumpstart the debug process by analyzing results across multiple tool runs.
  • How to reduce maintenance, improve automation and ensure your efforts are focused on verification and not environment infrastructure.​

 

Who Should Attend

  • Design and Verification Engineers
  • Design and Verification Managers

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