Date(s) - 03/29/2018
11:30 am - 12:30 pm



This webinar is focused on the practical applications of signal integrity analysis using HyperLynx SI. The webinar begins with classic signal integrity analysis topics and continues with a discussion of today’s high speed design challenges and methodologies needed for DDRx analysis and SERDES multi-gigabit channel design.

What You Will Learn

•Techniques of classic signal integrity analysis using HyperLynx LineSim

•Addressing post-route PCB verification using HyperLynx BoardSim
•The challenges involved with DDRx memory design verification
•Using multi-gigabit channel analysis for SERDES design

Who Should Attend

  •  Engineers and managers involved in high-speed system design — particularly in rapid prototyping environments where return on tool investment is critical
    •Anyone concerned about high-speed design — even if you’re not a signal integrity or EMI expert
    •Current HyperLynx customers who want to learn more
    •Design and Verification Engineers



Bookings are closed for this event.