Date(s) - 04/11/2019
11:30 am - 12:30 pm

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Setting up the proper design constraints and following these constraints when routing the board is critical for the high speeds involved in Double Data Rate (DDR) designs.  In this webinar we will discuss the routing constraints required for a DDR3/DD4 design.  We will demonstrate the organization of these constraints using Mentor’s Constraint Editing System (CES) in PADS Professional®, a fully integrated constraint-driven design methodology that reduces design costs and time-to-market by automating design rules communication.

We then go on to demonstrate routing the DDR design circuits and how PADS Professional helps you keep increasingly dense, complex PCB designs strictly constrained to design rules.  We will highlight the routing techniques that enable you to have more control and significantly greater productivity with manual-route quality.

Please join us for our webinar on how to manage your DDR3/DDR4 constraints and route them in Pads Professional.

What You’ll Learn

  • How to Precisely control classes, nets, groups, pin pairs, and more for DDR3/DDR4 using hierarchical rules
  • Defining high-speed rules for matched lengths, differential pairs, max/min length and more
  • Get direct validation of your layout against design intent through common, concurrent constraint editing including cross-probing using constraint templates that extend complex rules to multiple nets.
  • Enter constraints once and propagate throughout the design flow
  • How to use the advanced routing methods in PADS Professional to speed the design process
  • Ensure routes meet performance requirements with high-speed rules
  • Learn how to use tuning functions for length and phase matching

Who Should Attend

  • Board designers
  • Electrical engineers
  • Engineering managers