Date(s) - 07/26/2018
11:30 am - 12:30 pm
Code Coverage is a method used to determine the effectiveness of the testbench for a piece of HDL code, which it does by measuring and indicating what percentage of the design was exercised by this testbench. The concept originally came from the software world where this is used in almost every software development organization in their verification cycles. Despite the similarity of HDL code to software written in languages such as C, it is not so extensively used in HDL code verification.
Without code coverage the designer will find it hard (or impossible) to know if all aspects of the RTL code have been exercised by the testbench. Code Coverage is built into the simulator and it will tell the designer which areas have been exercised and, much more importantly, which have not. Without the use of Code Coverage it is highly likely that key parts of the functionality of a design have not been fully verified which leaves the possibility of bugs slipping through the scope of the regression tests.
What You Will Learn
- What Code Coverage is
- What it can tell you about your code and testbench
- How it can be used within your verification environment
Who Should Attend
- Design Engineers
- FPGA Designers
- Verification Engineers and their Managers
Bookings are closed for this event.