Date/Time
Date(s) - 04/09/2019
12:00 pm - 5:30 pm

Categories No Categories


Overview

Join Harry Foster, Tom Fitzpatrick and other Verification Academy experts to hear the latest updates on verification trends that are pushing the need for advanced verification.

Hear how users in the industry are adapting and taking a new look at verification methodologies to help build higher quality and more competitive on-time products in today’s evolving FPGA and ASIC markets. These sessions will discuss the most recent Wilson Survey on verification trends, the UVM Framework, a code base and generator used to implement verification infrastructure, interconnect, and operation. This includes writing constraints to characterize stimulus and configuration, creating prediction models, and defining coverage models with rapid testbench development utilizing the Questa Verification IP configurator to create high quality verification environments. In addition, learn about the ability of the Veloce platform for hardware-based acceleration and the full suite of Formal Apps and how they can be applied to a specific verification challenge in your organization.

What You’ll Learn

  • Understand how users in the industry are adapting
  • Take a new look at your verification methodologies to increase quality and timing
  • Discuss the UVM Framework
  • Learn writing constraints to characterize stimulus and configuration
  • Create prediction models
  • Define coverage models with rapid testbench development
  • Learn verification and analysis with emulation for hardware-based acceleration
  • Understand the usage of formal apps to boost your verification efficiency and design quality

Who Should Attend

  • Design and Verification Engineers and Managers

Agenda

12:00 PM Check-in and Lunch
12:30 PM A Tale of Two Technologies: ASIC & FPGA SoC Verification Trends
01:30 PM Don’t Do It Yourself: Questa VIP Accelerates UVM Testbench Development
02:15 PM Break
02:30 PM Making Verification Fun Again
03:15 PM Verification Acceleration for ASIC and FPGA Designs
04:00 PM No Testbench? No Problem: We Have a (Formal) App for That
04:45 PM Networking Reception

Bookings