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Customizing DDR4 Designs for Cost & Performance
This webinar will discuss the different design variables that can affect DDR design margin, and show how board and system designers can use HyperLynx pre-layout simulation to develop layout rules will optimize design margins and minimize cost.
Ensuring DDR4 Electrical Performance at Intended Data-Rate
This webinar will discuss the different electrical requirements associated with DDR designs and show how board and system designers can use HyperLynx to perform post-route verification themselves, helping free up scarce SI experts to focus on their company’s most challenging analysis problems.
Structure Function What Is a Structure Function
Structure functions are vital for investigating the integrity of your packages. Thermal transient testing performed by Simcenter T3STER and structure functions have become a widely accepted analysis tool. View this video to find out what structure functions are, the principles behind them and how they can support package characterization and reliability analysis.
Routing Capabilities You Need to Accelerate PCB Design Reliability
As a PCB designer, we're always looking for a better, faster and reliable way to get our job done. If the tool we're using does not have the required automation - we often end up using time consuming work-a-rounds to complete our projects.
Managing Electronics Systems Design Risk With An Optimized Verification Strategy
Most organizations leave detailed design validation for lab prototype testing, but this approach discovers problems late in the design cycle, leading to board re-spins that introduce delays and raise project costs. Increasing PCB systems performance requirements coupled with a pressure to improve product quality are driving engineering teams to consider alternatives to their current validation approach.
Addressing Challenges in Electronic Design Library Management
Xpedition® EDM provides a fully integrated PCB design data management infrastructure, from initial system definition through the design process, to release to manufacturing. It also supports seamless integration between engineering and PLM and ERP systems to provide full lifecycle management of your designs and libraries.
Addressing Challenges in Mixed Signal Design
Xpedition AMS enables engineers to do functional simulations not only for analog circuitry, but for mixed analog, digital, hydraulics, magnetics, thermal and mechanical motion.
Accelerate Your New Product Introductions with Valor NPI
Valor NPI has been the recognized leader in PCB DFM for many years. Many OEMs receive Valor DFM Reports from their CM when putting new PCB’s into production. But have you considered the benefits of doing those checks early in the process, before the PCB is placed and routed, making it very difficult to optimize for manufacturing? The latest revision of Valor NPI, V11.1 has a new methodology for rules handling and check setup, making it much easier for OEMs to do DFM in house, “Left Shifting” DFM in the introduction process, saving expensive revision spins and improving the quality of the final product.
Save Time Using Constraint Management - A Success Story
When advanced technologies are utilized in a design, more sophisticated rules and constraints are needed. Some constraints may be more physical, such as traces and nets that must be routed on a specific layer, or need to be restricted to a certain area of the board. These may be easy to keep track of manually for a few nets, but if you have hundreds, even thousands of complex constraints, you need an automatic way to manage and adhere to these during design.
PartQuest, paired with Digikey, can help you quickly build your library of symbols and footprints. Search through Digikey’s entire catalog of components to see what is available to download. Easily bring symbols, footprints, and parametric information into PADS Professional or Xpedition. If a part does not contain a symbol or footprint, you can request it to be made. View this webinar to learn how to setup and use this free service.
System Verilog Strategies
In this webinar, we will introduce to the VHDL/Verilog coders the basic structures of the SV language that form the core of an Advanced Verification Environment. Topics of discussion include SV basics, classes, interfaces, random constraints, and functional coverage. We also will introduce the strategies for implementing the Universal Verification Methodology (UVM) as the foundation to provide the structural and procedural building blocks of the modern, reusable testbench.
Questa Verification Management
When verification is not under control, project schedules slip, quality is jeopardized and the risk of re-spins soars. What’s required is a common platform and environment that provides all parties – system architects, software engineers, designers and verification specialists – with real-time visibility into the project. And not just to the verification plan, but also to the specifications and the design, both of which change over time.
PADS Designer Setup - Tips and Tricks
In this webinar we will go through the steps involved in setting up PADS Designer for either the netlist flow or integrated flow, and some tips and tricks for existing users.