Upcoming Events

May 28th, 2020

Ensuring DDR4 Electrical Performance at Intended Data-rate

Location: Webinar

This webinar will discuss the different electrical requirements associated with DDR designs and show how board and system designers can use HyperLynx to perform post-route...

Jun 4th, 2020

Customizing DDR4 Designs for Cost & Performance

Location: Webinar

This webinar will discuss the different design variables that can affect DDR design margin, and show how board and system designers can use HyperLynx pre-layout...

Jun 18th, 2020

Error Reduction in the Design Definition Phase

Location: Webinar

During this webinar we will be showing approaches to reduce errors in the design definition phase, reducing risks and overhead during schematic reviews.

Jul 9th, 2020

Optimize New Product Introductions - Going Fast, Right or Both

Location: Webinar

During this event, we will show how customers are using DFM embedded in the design tools, empowering designers to address all three priorities without compromise....

Jul 30th, 2020

A Hybrid Design Verification Methodology for Increased Coverage and Faster Interactions

Location: Webinar

This webinar discusses a hybrid approach for post-route verification that quickly and automatically screens designs for potential faults across multiple disciplines. Potential faults can then...