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| Trilogic carries a complete line of products to compliment your engineering and data management needs.
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| Displaying Category: ASIC Design |
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| The 0-In® CDC verification solution sets the industry benchmark by providing the three essential elements for a complete CDC verification solution: structural or static CDC analysis, CDC protocol verification, and CDC reconvergence verification. It is the only solution that gives you confidence that all your CDC bugs will be found and expensive respins avoided. | | Category: ASIC Design, FPGA Design | | Download Datasheet/Request Demo |
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| The 0-In® Formal verification solution offers the highest capacity and performance available along with a set of formal verification engines to help you find your most complex bugs. Together with the extensive CheckerWare® library of monitors and assertions and close integration with your simulation environment. 0-In® Formal represents the leading edge in formal verification, allowing you to not only improve overall verification quality but also find the most critical bugs in your design. | | Category: ASIC Design | | Download Datasheet/Request Demo |
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| Calibre® nmDRC is the solution to the physical verification challenges of nanometer design. Calibre nmDRC, with the new Hyperscaling processing architecture, produces best-in-class DRC run times with scalability to 100 CPUs. Full integration to popular layout environments and direct read capability allow designers to invoke DRC and debug results seamlessly within their design flow. Calibre nmDRC leverages the Calibre nm Platform to provide model-based verification and analysis, and visualization to guide the designer to the errors that truly impact yield. It is integrated with an innovative incremental verification and dynamic results viewing/debugging environment to further reduce DRC cycle time and dramatically improve designer productivity.
| | Category: ASIC Design, IC Design | | Download Datasheet/Request Demo |
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| Catapult is for ASIC and FPGA hardware designers of portable wireless, video, and image processing equipment who need to deliver optimal implementations with aggressive time-to-market requirements. Catapult is a high-level synthesis tool that uses industry-standard ANSI C++ to generate correct-by-construction, high-quality RTL 10-100x faster than other methods. Unlike traditional RTL design methodologies, Catapult enables the designer to pick the best architecture for given performance/area/power requirement and avoids the design errors introduced from hand coding the RTL description. | | Category: ASIC Design, C Based System Design | | Download Datasheet/Request Demo |
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| Codelink is an entirely new codebase developed from the ground up. There is zero Seamless content in Codelink. Codelink is a source-level debugger for RTL processor models like ARM’s design simulation model (DSM). It records batch runs and provides post-simulation debug, allowing the user to step forward or backward through code execution.
| | Category: ASIC Design, FPGA Design | | Download Datasheet/Request Demo |
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Product Features:
• Dramatically Reduces ASIC/FPGA Verification Time
• Compares two designs
- RTL to gate for synthesis and ECOs
- Gate to gate for layout spins
- RTL to RTL for language conversion
•Highest capacity tool
- Verifies multi-million gate ASIC's as one
•Fastest route to correct design
- Exact location of errors
- Tests fixes within the verification session
•Advanced FPGA Support
- Xilinx, Altera, Actel
- FVI and VIF automated setup files
- Huge productivity boost
| | Category: ASIC Design, DO 254/Safety Based Design | | Download Datasheet/Request Demo |
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| HDL Designer delivers solutions optimizing the design creation, synthesis and verification processes of advanced ASIC and FPGA designs in a team environment. | | Category: ASIC Design, DO 254/Safety Based Design, FPGA Design | | Download Datasheet/Request Demo |
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| inFact intelligently generates simulation sequences, data, and checks from a concise behavioral description of a design's specification, achieving high functional coverage at the module, subsystem, and system levels - resulting in a 10x gain in overall verification productivity. | | Category: ASIC Design | | Download Datasheet/Request Demo |
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| Questa is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow. | | Category: ASIC Design, FPGA Design | | Download Datasheet/Request Demo |
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| Vista™ is the industry's most advanced SystemC debug toolset, providing powerful hardware and C/C++ oriented views and debugging mechanisms. Vista dramatically reduces ESL and SystemC debugging cycles and enables hardware engineers to effectively trace C/C++ constructs within a familiar hardware debugging platform. Transaction level modeling is supported without instrumentation while providing designers with unique debug functionality and viewers. Vista naturally links into any SystemC environment and mixed-language simulation kernels including Questa, Incisive, and OSCI. | | Category: ASIC Design, C Based System Design | | Download Datasheet/Request Demo |
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