Transistor level simulation takes hours for large blocks. This is a problem for design and verification. You can reduce your simulation time from hours to minutes and overcome limitations by enhancing your behavioral models with WiCkeD generated Response Surface Models (RSM).

MunEDA's WiCkeD toolset is a performance and yield optimization toolkit with modeling functionality that is easy to use and integrates with the industry leading standard design frameworks and SPICE simulators to provide the best result in the shortest time. The WiCkeD tools have proven themselves on projects and silicon at leading IC companies like Samsung, STMicroelectronics, Infineon, Altera, ON Semiconductor, Hynix, ST-Ericsson and many others to greatly increase the efficiency of designers to achieve the best balance between circuit performance and yield for the specific application. It does this by providing a toolset with state of the art analysis and optimization tools supporting the creative work of analog designers.

Feature highlights are:
• How an existing spice-behavioral model co-simulation can be enhanced using WiCkeD modeling
• How WiCkeD can again be applied to the co-simulation for analysis (or optimization)
• A live demo featuring the simulation, verilogA code changes, WiCkeD run to generate the model

This webinar will give an overview of the WiCkeD Modeling Toolset.

Who Should Attend:
• Analog/Mixed Signal IC Design Engineers
• IC Design Managers
• CAD Engineers & Managers
• IC Library Engineers
For more information on MunEDA, please visit their website at www.muneda.com