Enhancing Electronic Design Productivity and Enabling New Technologies Search:   Contact Us  |  1.978.658.3800 Company | Products | Solutions | News & Events | Support | Vendors Overview | Contact Us | Directions | Career Opportunities | Facts Product List | Information Request Overview | ASIC Design | Board Level Design | Board Level Manufacturing | Data Management - PLM | C Based System Design | DO 254/Safety Design | FPGA Design | IC Design Overview | Training Classes | Events | News Overview | Training Classes Overview | Mentor Graphics | Omnify Software | PADS | DownStream Technologies | Temento Systems | MunEDA | ModelSim | Gate Rocket News & Events Overview Training Classes Events News » Event Registration   Quick Links » Home Page » Contact Us » Solutions Event Registration Please fill out the brief form below to register for the specified event Registration Form * Event: HyperLynx Hands On Workshop 9/21/10 Melbourne, FL (Workshop) - 9/21/2010 2010 Omnify Software User Conference - Empower '10 (Seminar) - 9/22/2010 HyperLynx Hands On Workshop St Petersburg, FL 9/23/10 (Workshop) - 9/23/2010 Eptech - Quebec City (Seminar) - 9/23/2010 Eptech Show - Winnepeg (Seminar) - 10/19/2010 Controlling Crosstalk in High Speed PCB Design (Webinar) - On-Demand Design for Performance: Advanced Simulation and Verification in PCB Development (Webinar) - On-Demand S-Parameters: Are They as Good as You Think? (Webinar) - On-Demand Bringing SERDES Simulations to the Next Level with Mentor's Fast Eye Technology (Webinar) - On-Demand Add Mixed Technology, including RF to Your PCB Design in Half the Time (Webinar) - On-Demand Reduce Cycle Time by Over 60% in PCB Placing and Routing (Webinar) - On-Demand DDR2 Do's and Don'ts On Demand Webcast (Webinar) - On-Demand Introduction to I/O Designer (Webinar) - On-Demand Optimize System Performance with FPGA/PCB Co-Design (Webinar) - On-Demand Webinar: Bringing SERDES Simulations to the Next Level with Mentor's Fast Eye Technology   Date: On-Demand    Duration: 1 day(s)    Location: Online The low BER requirements of high-speed differential signalling on busses such as PCI Express, SATA, and FibreChannel have brought about the need for exhaustive eye diagram analysis. Traditional methods of time-domain simulation are impractical for verifying BER requirements of 1e-12 and lower. Fast Eye from Mentor Graphics solves this problem by providing such eye diagrams in hours instead of days or weeks of simulation. We will discuss the methods used to generate the simulation data, including prediction of the worst-case bit sequence on the channel. In this 30-minute web seminar, you will learn how Mentor's Fast Eye technology is changing the way SERDES busses are simulated, allowing for validation of channel performance down to the 1e-15 BER level and beyond. * First Name: * Last Name: * Email: * Company: Title: Country/State: Phone: Comments:   Privacy Policy  |  About Us  |  Site Map  |  ©1986-2008 Trilogic, Inc.