Trilogic, Mentor Graphics, Altera, and Arrow cordially invite you to attend a FREE "Hands On Workshop" focused on Signal Integrity Analysis using HyperLynx 8.0 simulation of Altera's technologies.

This is a technology focused workshop that provides attendees with education and practical experience.

Session one of the Hands On Workshop begins with a review of the basic signal integrity analysis using HyperLynx 8.0 simulations of interconnect technologies. It continues with a discussion of the effects of increasing clock and data rates, and faster component edge rates on designs.

Session two Altera will provide an update of their FPGA families. A presentation will also be given on the HyperLynx Design Kits available from Mentor and Altera.

Session three continues with a discussion of high speed GHz interconnect simulation, and comparison of synchronous vs. asynchronous design technologies. We will focus on multi-gigabit design issues such as enhanced via and connector modeling, lossy transmission line analysis, multi-bit stimulus, and the use of eye diagrams and eye masks.

Session four GateRocket will present “Device Native Verification for Altera Stratix”. GateRocket solutions bring FPGA in to the simulator and particularly enables verification of SERDES applications.

Session five continues with a discussion of the new DDRx Wizard in HyperLynx 8.0. DDR2 and DDR3 are the most common memory interfaces in the industry today. A discussion of the complexities and challenges of validating this interface will include topics such as On-Die-Termination, signal de-rating, fly-by-architecture and READ/WRITE signal leveling. For this example we will walk through the setup of the DDRx Wizard in HyperLynx 8.0 and run simulations to validate the DDRx memory interface.

Session six will be a short overview of Mentor Graphics newly released HyperLynx PI for power integrity. We will discuss DC drop analysis, decoupling and plane noise analysis.

A FREE lunch will be provided during the event. Seating is limited, so register now to reserve your space. We will send you an email to confirm your registration and attendance and provide directions.

Who Should Attend:
Engineers and managers involved in high-speed system design -- particularly in rapid prototyping environments where return on tool investment is critical
Anyone concerned about high-speed design -- even if you're not a signal integrity expert
Current HyperLynx customers who want to learn about our newest release, v8.0 and HyperLynx for Power Integrity
Design and Verification Engineers