Date(s) - 03/22/2018
11:30 am - 12:30 pm


The Evolution of FPGA Verification and How to Address Today’s Challenges
Web Seminar
Thursday March 22, 2018


Ever since the advent of digital RTL design in the early nineties, designers have also need to verify these designs.   With the ever increasing complexity of these designs, driven by Moore’s law, achieving first pass success is an ever increasing challenge.  The costs of failure in an ASIC project are obvious (respin NREs in the $100Ks or more, months of schedule slip, just to name a few).  The costs in an FPGA project while possibly not as obvious can be just as detrimental (late product introduction missing the market window, field product issues tarnishing brand).

In this seminar we will look at the history of digital verification. We will review identify challenges of traditional approaches. We will look at how new technologies such as assertions, constrained randomization, algorithmic testbench design and formal verification are attempting to solve  these challenges.  Finally we will maps these new technologies to solutions created Mentor Graphics.

Who should attend:

  • Digital ASIC/FPGA designers
  • Verification Engineers
  • Project Managers