Date/Time
Date(s) - 05/17/2018
11:30 am - 12:30 pm

Categories


Overview

Beyond the design-specific technical challenges that are associated with designing and analyzing a Serialization – Deserialization (SERDES) interconnect, hardware engineers face industry-related complexities. For example, unlike the relative simplicity of a few double data rate (DDRx) specifications, there are more than 100 unique SERDES specifications. For printed circuit board (PCB) design, in the past the lack of knowledge of these protocols meant interconnect analysis had to start from scratch for every protocol.

In this webinar, we will look at the SERDES design and analysis capabilities found in HyperLynx from Mentor Graphics.  We will review the steps involved in SERDES analysis including intelligent, automatic channel extraction, interface-level channel compliance verification, pre-layout design exploration, and post-layout verification.  We will demonstrate how the recently released SERDES Wizard simplifies the process of validating the multiple available SERDES protocols.

What You Will Learn  

  • Pre-layout compliance testing with SerDes Compliance Wizard
  • Channel extraction and analysis, even before models are available
  • Design space exploration with 3D Explorer and sweeps
  • Post-layout IBIS AMI simulation directly in BoardSim

Who Should View

  • Signal Integrity Engineers
  • Electrical Engineers
  • PCB Engineers

Engineering Manager

 

Bookings

Bookings are closed for this event.