Date/Time
Date(s) - 05/31/2017
11:00 am - 12:00 pm

Categories


Breaking the Speed Limits on SoC Verification with the Questa Flow
Web Seminar
Wednesday May 31, 2017
11am – 12pm

Overview
As SoC designs are evolving and growing in complexity to match the capabilities of today’s ASIC and FPGA technologies, so too are the testbenches and verification flows built around those designs. They are complex Software Engineering projects in their own right.

There are new criteria driving evolution in complexity – such as concurrent DUT stimulus, multi-level reuse of components and sequences, portability from simulator to emulator enabled by today’s emulator architecture, and increasingly common is that design/verification teams are split across locations and geographies, collaborating on mega-gate designs.

That kind of development requires speed – speed of execution, speed of turnaround, and ultimately speed of the tools in the flow. What is needed is a simulation build/regression flow where the tools are optimized for maximum speed, and maximum turnaround time.

In this session, you will learn best practice in verification flows in the industry today, and how to implement the optimal flow to speed your SoC design verification cycle.

Who Should Attend

  • ASIC/IC/FPGA Verification Engineers

  • Project Leads

  • Managers

What You Will Learn

  • Block-, Subsystem-, and SoC-level verification flows in common use in the industry today

  • How best practice in design of the verification flow leads to improved productivity

  • How Mentor’s Questa® Simulator is providing highest performance across the flow

Products Covered

Bookings